医用集成电路(IC) 品牌:XILINX 型号:XC2C384-10TQG14 产地:国外·美国 产品注册号:无 用途: 医用 招商状态:招商中 招商区域:全国 浏览量:24052 | 深圳市睿宇兆恒科技有限公司 联系时请告知消息来自3618医疗器械网,您会获得更多的优惠或支持 联系人:****** 联系电话:****** |
XC2C384-10TQG144C 赛林斯CPLD
原装进口美国赛林斯 XC2C384 CoolRunner-II 系列 复杂可编程逻辑器件
Desc[x]ription
The CoolRunner-II 384-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reliability is improved
This device consists of twenty four Function Blocks
inter-connected by a low power Advanced Interconnect
Matrix (AIM). The AIM feeds 40 true and complement inputs
to each Function Block. The Function Blocks consist of a 40
by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be
configured as direct input registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchronously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation ba[x]sed on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
更多 医用集成电路(IC) 价格、说明、厂家,请关注3618医疗器械网* 温馨提示:请仔细阅读产品说明书或在医务、专业人员指导下购买和使用,禁忌内容或者注意事项详见说明书。